The present invention is directed to full duplex bidirectional communication systems and, more particularly, to an integrated electronic circuit for separating transmit data from receive data in a high-speed bidirectional data transmission line such as gigabit Ethernet.
The past few years has witnessed an almost exponential growth in the extent of high speed data networks, and the data transmission speeds contemplated over such networks. In particular, bidirectional data transmission in accordance with the various Ethernet network protocols, over unshielded twisted pair (UTP) wiring, has emerged as the network implementation of choice for general commercial LAN installations as well as for some of the more prosaic residential and academic applications.
Local Area Networks (LAN) provide network connectivity for personal computers, workstations and servers. Ethernet, in its original 10BASE-T form, remains the dominant network technology for LANs. However, among the high speed LAN technologies available today, Fast Ethernet, or 100BASE-T, has become the leading choice. Fast Ethernet technology provides a smooth, non-disruptive evolution from the 10 megabits per second (Mbps) performance of the 10BASE-T to the 100 Mbps performance of the 100BASE-T. The growing use of 100BASE-T connections to servers and desktops is creating a definite need for an even higher speed network technology at the backbone and server level.
The most appropriate solution to this need, now in development, is Gigabit Ethernet. Gigabit Ethernet will provide 1 gigabit per second (Gbps) bandwidth with the simplicity of Ethernet at lower cost than other technologies of comparable speed, and will offer a smooth upgrade path for current Ethernet installations. However implemented, the latest high-speed Ethernet protocols contemplate simultaneous, full bandwidth transmission, in both directions (termed full duplex), within a particular frequency band, when it is desirable to maximize transmission speed. However, when configured to transmit in full duplex mode, it is evident that the transmitter and receiver sections of a transceiver circuit must be coupled together, in parallel fashion, at some transmission nexus short of twisted pair transmission channel.
Because of the nexus coupling together of the transmitter and receiver, it is further evident that the simultaneous assertion of a receive signal and a transmit signal, on the transmission nexus, will cause the receive signal to become substantially impaired or modified in the absence of some methodology to separate them.
Standard arrangements for achieving this isolation or transmit/receive signal separation in the prior art include complex hybrid circuitry provided as a separate element external to an integrated circuit transceiver chip. Hybrids are generally coupled between the transmit/receive signal nexus (the channel) and the transmit and receive signal I/Os, as depicted in the generalized system diagram of FIG. 1.
FIG. 1 illustrates a simplified block diagram of a multi-pair communication system operating in conformance with the IEEE 802.3 standard (also termed 1000BASE-T) for 1 gigabit (Gb/s) Ethernet full-duplex communication over four twisted pairs of Category-5 copper wires. The communication system illustrated in FIG. 1 is represented as a point-to-point system, in order to simplify the explanation, and includes two main transceiver blocks 2 and 3, coupled together with four twisted-pair cables 4a, b, c and d. Each of the wire pairs is coupled between transceiver blocks through a respective one of four hybrid circuits 5 and communicate information developed by respective ones of four transmitter/receiver circuits (constituent transceivers) 6 coupled between respective hybrid circuits and a Physical Coding Sublayer (PCS) block 8 Each of the four constituent transceivers 6 are capable of operating simultaneously at 250 megabits per second (Mb/s), and are coupled through a respective hybrid circuit to facilitate full-duplex bidirectional operation. Thus, 1 Gb/s communication throughput of each of the transceiver blocks 2 and 3 is achieved by using four 250 Mb/s (125 Mbaud at 2 bits per symbol) constituent transceivers for each of the transceiver blocks and four pairs of twisted copper cables to connect the two transceivers together.
A hybrid circuit is basically an externally coupled electrical bridge circuit including costly magnetic elements which isolates the transmit signal path from the receive signal path when the circuit is in a balanced condition. In such hybrid circuits, the balance condition requires that the terminating impedance equal the impedance of the channel (a twisted pair cable) for any significant degree of isolation or signal separation. Since this impedance is dynamic, and since the frequency dependent nature of this dynamic impedance is complex and not readily reproducible, only an approximate cancellation is achieved in practice. Direct leakage across the hybrid circuit and delayed echoes caused by impedance and timing mismatches will thus cause transmitter signal components to interfere with a received distant signal. The effect of this echo is particularly apparent, and particularly problematic, as transmission speeds increase.
Although small amounts of impedance mismatching is tolerable for analog voice applications, real-time, full duplex data transmission requires that the amount of hybrid echo be minimized. One method of dealing with the more stringent requirements of real-time, full duplex data transmission, is to substantially increase the complexity of any hybrid circuit coupled between the transmission channel, the transmit DAC and the receive ADC of a transceiver system; some transceiver circuits going so far as to implement both single-ended and differential hybrid circuits.
Notwithstanding the foregoing, local hybrid echo represents a serious impairment to receive signals in high speed, full duplex data communication devices. Indeed, the local hybrid echo path model is commonly used to assess a particular echo level in a transceiver/channel system and as a reference for design of down-stream echo cancellation circuitry. In addition to excess complexity and non-linear response, hybrid circuits represent costly, marginally acceptable solutions to the transmit/receive signal separation issue.
It would be beneficial, both to circuit performance and to manufacturing economies, if a local transmit signal were to be separated from a receive signal, in full duplex operation, without the need for complex and costly hybrid circuitry. Such separation should be accommodated by circuitry resident on an integrated circuit transceiver chip and in relative proximity to the signals being processed. Such separation should further be performed in a substantially linear fashion, i.e., frequency independent, and be substantially immune to semiconductor process tolerance, power supply and thermal parameter variations.
A bidirectional communication system is configured for full duplex communication over a communication channel. The system is constructed to incorporate a main transmitter having an output for serving a transmit signal on a transmit signal path electrically coupled between the communication channel and the output of the transmitter. The system also incorporates a receiver having an input connected to a receive signal path electrically coupled to the communication channel for receiving a receive signal. A transmit signal cancellation circuit is electrically coupled to the receive signal path, and develops a cancellation signal, which is an analogue of the transmit signal, which is asserted to the receive signal path so as to prevent the transmit signal from being superposed on a receive signal at the input of the receiver.
The transmit signal cancellation circuit incorporates first and second replica transmitters, each of which are connected to and operatively responsive to a digital word representing an analog signal to be transmitted. The first replica transmitter is coupled to the receive signal path and develops a voltage mode signal which is equal to but opposite in phase of a voltage mode portion of the transmit signal. The second replica transmitter is also coupled to the receive signal path and develops a current mode signal having a direct phase relationship with the transmit signal. The voltage mode and current mode signals are combined with the transmit signal on the receive signal path and, in combination, cancel voltage and current mode components of the transmit signal that might appear at the inputs of the receiver during simultaneous transmission and reception.
In one particular aspect of the invention, the main transmitter and the first and second replica transmitters are constructed as current mode digital-to-analog converters. The main transmit DAC outputs a differential analog current mode signal which is converted to a differential voltage mode signal by a load impedance incorporated in a line interface circuit. The first replica DAC outputs a first analog differential current mode signal which is converted to a voltage mode signal by a cancellation impedance circuit coupled into the receive signal path between the first replica DAC and the output of the main transmit DAC.
The second replica DAC also outputs a differential analog current mode signal to the receive signal path. The current mode signal provided by the second replica DAC is provided in order to compensate for excess current sourced/sunk to the signal path by operation of the first replica DAC.
In a further aspect of the invention, an integrated circuit transceiver separates transmit data from receive data in a bidirectional communication system by use of two replica DACs, a positive replica DAC and a negative DAC, each constructed to perform identically to a main transmit DAC except for a gain function. The negative replica DAC in combination with a cancellation impedance, generates a cancellation voltage which is subtracted from a transmit signal. The positive replica DAC generates a cancellation current which is subtracted from the sum of the cancellation voltage and the transmitted signal so as to compensate for excess current developed by the negative replica DAC. Thus, two matched replica DAC transmitters isolate a transmission signal from the receiver while maintaining a balanced transmission voltage and current at a transmission channel load. A cancellation voltage, equal to the output voltage of a main transmit DAC is generated by one of the replica transmitters across a cancellation impedance circuit. The cancellation voltage is subtracted from the output voltage of the main transmit DAC. The second replica DAC transmitter generates a cancellation current equal to the current generated by the first replica DAC transmitter so as to maintain said balanced transmission voltage and current at the load.